Current technology trends continue to focus on high performance CMOS (complementary metal-oxide-semiconductor) and a new arena of VLSI (very-large-scale integration) called Smart Power chips is being developed. Smart Power chips are built with both low and high voltage CMOS. Power transistors on these Smart Power chips typically allow operating voltages up to 40 volts. The thrust of current research focuses on improving the transistor performance.
Smart Power chips are widely used in the automotive industry. The automotive environment is harsh and requires relatively high levels of protection against ESD and other types of transients. However, power transistors are generally weak for ESD due to their inherent device structure. Good ESD performance actually requires low power dissipation capability under high currents. This is inherent in optimized NMOS transistor structures, but not in power transistors due to the fact that the holding voltages are quite high. A high holding voltage increases the relative power dissipation under an ESD event and results in a low self-protection level.
A prior-art DEnMOS power transistor is shown in FIG. 1. The DEnMOS is built on in a p-tank 112 located in a p-type epitaxial substrate 110. The drain 116 is formed in a n-well 114. The source 118 is formed directly in the p-tank 112. The gate 120 is located partially over the p-tank and partially over a field oxide region 122 that is located between the drain 116 and the source 118. A 500 .ANG. gate oxide 122 is located between the gate 120 and the p-tank 112. Typical channel lengths (between the source 118 edge and the n-well 114 edge) are 3-4 .mu.m. Smaller than 3 .mu.m channel lengths are not used because the breakdown voltage (BVdss) would be lowered for high voltage applications. Under drain avalanche, the gate oxide region 122 does not breakdown since part of the voltage is supported by the depletion in the n-well 114.